In modern electronic circuits, such as, for example, high-speed interface circuitry, receivers, transmitters, analog-to-digital and digital-to-analog converters, data recovery circuitry, etc., it is desirable to reduce the variation in received clock signals. Unfortunately, in practical systems, clock signals do not arrive precisely at the same time in a spatial or even temporal reference. A clock signal that arrives slightly out of phase at difference spatial locations is often referred to as being skewed. Similarly, jitter often refers to variation in the arrival of the clock signal relative to an average arrival time (e.g., clock period) from cycle to cycle; thus, jitter can be defined as the timing error of a digital signal.
When dealing with jitter in a given system, it is often useful to classify the different types of jitter that can occur. The composite, overall jitter associated with a data signal is typically referred to as total jitter. Total jitter may be thought of as being composed of a number of different components resulting from various noise and signal sources within the system. These jitter components are generally classified into two primary categories: deterministic jitter and random jitter. Most jitter components are not truly random in a statistical sense, and thus fall into the deterministic category. More particularly, most digital signals have regular time intervals at which voltage level transitions occur. When the digital signal is compared to an ideal periodic waveform, the effects of jitter are noticeable.
In an input/output (I/O) interface application (e.g., I/O buffer and driver circuitry), voltage level translation circuitry has been shown to be a primary contributor to total jitter in a system. Thus, by improving the performance of the interface circuitry, a significant reduction in overall jitter in the system can be advantageously achieved.